Modern systems today require fast and accurate ADCs. That is to say, modern systems utilize ADCs that sample large numbers of bits at high frequencies. Examples of such modern systems include high speed communication systems and digital signal processor (DSP) applications.
One development in the art increases the sampling rate of an ADC by interleaving multiple slower ADCs, and adding a different phase offset to the clock at the input of each of the multiple slower ADCs. By interleaving the samples, an overall sampling rate is achieved that is equal to the product of the total number of interleaved ADCs and the individual sampling rate of each of the ADCs.
The above describe arrangement is referred to simply as an interleaved ADC. Although the sampling rate of an interleaved ADC is higher than a conventional single ADC architecture, there is a problem with the interleaved ADC. Specifically, in an interleaved ADC mismatches are introduced between different ADC branches including a timing offset that is sometimes referred to as timing skew. It should be noted that the terms “mismatch”, “timing mismatch”, “skew”, “timing skew”, “offset”, and “timing offset” may be used interchangeably in this disclosure.
In order to achieve high performance and high speed with an interleaved ADC, it is necessary to resolve the problem of timing skew. One way of resolving the problem is by estimating the timing skew, and then correcting the skew in either of the analog or digital domains. Embodiments disclosed herein therefore relate to estimating the timing skew by relying on cross-correlations between adjacent ADC branches.
There are several advantages to the embodiments disclosed herein. Initially, the complexity of an interleaved ADC as disclosed herein remains very low. Additionally, the estimation of the skew (and subsequent correction thereof) in each of the interleaved ADCs can be performed with very few limiting conditions as to the properties of input analog signals being sampled. Finally, an identification of the type of input signal is not required such that the estimation of the timing skew is referred to as being “blind.”